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In this paper, a novel triple reduced surface field (RESURF) LDMOS with N-top layer based on substrate termination technology (STT) is proposed. The analytical models of surface potential, surface electric field, breakdown voltage (BV) and optimal integrated charge of N-top layer (Qntop) for the novel triple RESURF LDMOS are achieved. Furthermore, STT is applied to avoid the premature avalanche breakdown...
An analytical model is proposed to describe the on-state current in linear and saturation regions for the high-voltage C-SenseFET. As C-SenseFET is an important sensing and charging integrated device, two key parameters–-sensing ratio K and charging swing factor α are analyzed in detail and some optimizational structures are provided. For the practical application of C-SenseFET, K and α are required...
An ultra-low Ron, sp SOI LDMOS with an improved BV is proposed and its breakdown mechanism is investigated. The device features a variable-k dielectric trench and a P-pillar beside the trench (VK-P). The P-pillar extending from the P-body to the trench bottom not only acts as the vertical junction termination extension (JTE), but also forms an enhanced vertical RESURF (reduced surface field) structure...
A novel substrate-assisted (SA) RESURF technology aiming at improving off-state breakdown voltage (BV) of PN junction with small curvature radius is proposed and experimentally demonstrated in this paper. The SA RESURF technology not only realizes small curvature radius in the fingertip region, but also reduces electric field concentration in the curved metallurgical junction. Low-doped P-substrate,...
A superjunction LDMOST with a floating oppositely doped buried layer in p-substrate is proposed. The buried layer provides another pn junction to sustain drain voltage, reduces the substrate-assisted-depletion effect and generates new electric field, which modulates the bulk electric field in off-state. Simulation results show that the proposed structure achieves significant breakdown voltage improvement...
A new Membrane PSOI High Voltage Device with a Buried P+ layer (MBP+ PSOI) is proposed. Breakdown voltage is only decided by lateral breakdown voltage because of the entire removing of silicon substrate under the drift region and breakdown voltage can be improved with increase of the length of the drift region. Introducing of P+ layer can effectively reduce specific on-resistance and silicon window...
A novel non-uniform multi-reversed-junction power MOSFET is presented in this paper. The high and uniform electric field in substrate is achieved due to modulating from space charges in the buried layers during operation in the blocking mode, and the breakdown voltage is improved considerably. A detailed study of the influence of various important parameters on blocking characteristics was carried...
A novel SOI high voltage device with a ring drain is developed. Junction curvature is introduced to enhance the breakdown voltage. As an example, Breakdown voltage over 600 V is achieved in a SOI LDMOS on the SOI material with 3 mum buried oxide and 20 mum silicon. Compared with normal structure, the breakdown voltage is increased by 6.74% and the on resistance is increased merely by 2.14%.The ring...
A new super junction LDMOS (SJ-LDMOS) on partial silicon-on-insulator (SOI) with composite substrate is presented in this paper. The thin super junction structure on the buried oxide (BOX) provides the surface low on-resistance path, which is attributed to the heavy doping trait of SJ. The N-buffer layer is introduced under the BOX to sustain vertical voltage, which reduces the substrate-assisted...
REBULF (reduced bulk field) and ENDIF (enhanced dielectric layer field) technologies are used in the design of lateral power devices to improve breakdown voltage. The two technologies have been shown to offer good performance in a variety of application domains, both in bulk silicon and SOI substrates. This paper aims to offer a compendious and timely review of the two technologies and some works...
In this paper, a novel substrate engineered power MOSFET with partial floating buried-layer is proposed. The proposed LDMOS with 2 mum thin epitaxial layer is designed . It is demonstrated that new electric field generated by the buried-layer modulates electric field in drift region and the voltage handling capability is enhanced. Influences of length, thickness and doping concentration of the buried-layer...
A new CMOS compatible super junction LDMSOT structure is designed with N+-floating layer embedded in the high-resistance substrate, which suppresses charges imbalance effect resulting from substrate-assisted depletion N-type pillar, and the high electric field around the drain is reduced by N+-floating layer which causes the redistribution of the bulk electric field in the drift region. The new structure...
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