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This paper presents an efficient approach to verifying higher-degree Galois-field (GF) arithmetic circuits. The proposed method describes GF arithmetic circuits using a mathematical graph-based representation and verifies them by a combination of algebraic transformations and a new verification method based on natural deduction for first-order predicate logic with equal sign. The natural deduction...
This paper presents a graph-based approach to designing arithmetic circuits over Galois fields (GFs) based on a polynomial ring (PR) representation, which is a redundant representation for GF arithmetic. The proposed method extends a graph-based circuit description, called a Galois-field arithmetic circuit graph (GF-ACG), which was originally proposed for no redundant GF arithmetic. First, the extension...
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