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In this paper, we propose a parameterized digitally controlled oscillator that can produce oscillating-clock signal with the tunable frequency covering an entire designated range. Moreover, we formulate the all-digital phase-locked loop optimization process as a search problem, during which we can find a good configuration that not only meets the user-defined requirement but also achieves a smaller...
In this paper, we introduce a systematic power analysis framework for SoC designs using bottom-up power modeling integrated with top-down power estimation. Four power analysis tools have been realized: (1) PowerBrick, a power characterization tool to construct power libraries for standard cell library and memory compiler, (2) PowerMixer, an RTL/gate-level power estimator for large logic design, (3)...
In this paper, we introduce an integrated power methodology for multi-core SoC designs. It features not only a bottom-up IP-based power modeling for all kinds of IP components ranging from hardware accelerators, processors, and memory blocks, but also a top-down system-wide ESL power estimation formulation. By linking these two methods of different levels of abstraction, one can thereby easily profile...
In this work, we propose a fast and accurate system-level power estimation methodology. To achieve high accuracy for an in-house digital signal processor, called PAC, we incorporate a hybrid power modeling scheme integrating three different levels of power models (including the instruction-level power model, the memory power model, and the transaction-based power model). These models are built using...
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