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The growing prominence and computational challenges imposed by Deep Neural Networks (DNNs) has fueled the design of specialized accelerator architectures and associated dataflows to improve their implementation efficiency. Each of these solutions serve as a datapoint on the throughput vs. energy trade-offs for a given DNN and a set of architectural constraints. In this paper, we set out to explore...
We demonstrate a novel FPGA-based accelerator architecture that can tackle a range of standard computer vision (CV) problems, with scalable performance and attractive speedups. The architecture relies on multiple pipelined processing elements (PEs) that can be configured to support various belief propagation (BP) settings for different CV tasks. Inside each PE, innovative implementation of Jump Flooding...
A real-time hardware-based large vocabulary speech recognizer requires high memory bandwidth. We have developed a field-programmable-gate-array (FPGA)-based 20 000-word speech recognizer utilizing efficient dynamic random access memory (DRAM) access. This system contains all the functional blocks for hidden-Markov-model-based speaker-independent continuous speech recognition: feature extraction, emission...
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