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DC-Step-Stress-Tests of GaN HEMTs have been performed on wafers with and without GaN-cap. The tests consist of a step ramping of drain-source voltage VDS by 5 V every two hours at off-state. The irreversible evolution of leakage current starting at a certain drain voltage has been taken as a criterion for the onset of device degradation. It has been stated that there is a stability limit for VDS depending...
Rapid prototyping options provided by backside FIB preparation are expanded by trimming device delay to the desired quantity. Using inverter chains in 180 nm standard CMOS technology, proper FIB backside treatment is demonstrated to speed up or slow down devices by more than 20%. This result agrees well with device simulations and applies in principle to any technology. Devices from a 65 nm strained...
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