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Electrical data of advanced capacitor dielectrics such as Sr-rich (Sr/(Sr + Ti) ~ 62%) strontium titanate (STO), rutile TiO2, which have dielectric constants higher than 60 even with physical thicknesses in the 7-10 nm range are presented. A practical capacitor model is proposed based on planar metal insulator-metal (MIM) system fabricated using 300 mm toolsets to access required capacitor dielectrics...
We establish a new record low leakage (JG)-EOT for DRAM compatible MIMcap by further JG reduction to 2×10−8 (10−7) A/cm2 at 0.45 (0.40) nm EOT (0.8 V) using an improved RuOx/TiOx/Sr-rich SrxTiyOz (STO) stack. Further, for the first time we provide insight explaining the origin of the record low JG-EOT achieved, by detailed studies of our TiOx/STO stack on TiN, Ru and RuOx bottom electrodes (BE). TiO...
We report the lowest leakage achieved to date in sub-0.5 nm EOT MIM capacitors compatible with DRAM flows, showing for the first time a path enabling scalability to the 3X nm node. A novel stack engineering consisting of: 1) novel controlled ultrathin Ru oxidation process, 2) TiOx interface layer, is used for the first time to achieve record low Jg-EOT in MIM capacitors using ALD Sr-rich STO high-k...
We demonstrate for the first time record low Leakage-EOT (3.5 times 10-7 A/cm2 at 1V, EOT=0.49 nm) MIM capacitors fabricated using a low temperature (250degC) ALD SrTiO3 (STO) deposition process on ALD TiN bottom electrode. While most previous work on STO used deposition techniques not compatible with high aspect ratio DRAM applications, recent work on ALD STO showed promise on noble-like metal electrodes...
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