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A pare to optimal temporal partition methodology was developed for splitting and mapping large data flow graph (DFG) to the coarse-grained reconfigurable architecture (CGRA). A multi-objective genetic algorithm (MOGA) derived from the SPEA-II algorithm was first time introduced to the temporal partition realm for simultaneously optimizing multiple mutually exclusive objectives. Experiments carried...
Reconfigurable processor is widely used in multimedia applications. Its performance depends not only on good hardware design but also on compilers that can quickly create efficient configurations. This paper describes an automatic compilation flow for REmus—a coarse-grained reconfigurable processor. The front-end of the compiler extracts code sections with high parallelism degree from the application...
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