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This research proposed a new type of memory cell designed by using only nMOS transistors. The memory cell consumes less power and also occupies minimum amount of silicon area. The stability of the data during successive read operation and noise margin are in the promising range. Extensive simulation results demonstrate the validity and competency of the proposed cell.
This research proposed a new design of memory cell of 7T SRAM using 16nm and 45nm (Arizona State University Predictive Technologies Model) PTM models. The memory cell provides larger static noise margin in hold state and a better read operation by controlling drain induces barrier lowering (DIBL) effect. With utilization of a single transistor, proposed cell provides stability of the data not only...
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