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Designing VLSI circuit using dynamic logic is one of the most area efficient techniques. However, the performance of the dynamic logic is not so promising due to longer time delay and higher leakage power. This research proposes a new model of dynamic logic by incorporating nMOS based resistive gate circuit. The proposed circuit reduces the contention time delay and the leakage power. Extensive simulation...
Dynamic logic is most area effective technique for designing VLSI circuit. However, due to lower noise margin of dynamic logic performance is not auspicious. This research proposes a N-FinFET based resistive keeper circuit using 45nm PTM FinFET model which reduces the contention between pull down network and keeper device using the special feature of four terminal FinFET (capacitance merging among...
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