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This research proposed a new type of memory cell designed by using only nMOS transistors. The memory cell consumes less power and also occupies minimum amount of silicon area. The stability of the data during successive read operation and noise margin are in the promising range. Extensive simulation results demonstrate the validity and competency of the proposed cell.
Designing VLSI circuit using dynamic logic is one of the most area efficient techniques. However, the performance of the dynamic logic is not so promising due to longer time delay and higher leakage power. This research proposes a new model of dynamic logic by incorporating nMOS based resistive gate circuit. The proposed circuit reduces the contention time delay and the leakage power. Extensive simulation...
Dynamic logic is most area effective technique for designing VLSI circuit. However, due to lower noise margin of dynamic logic performance is not auspicious. This research proposes a N-FinFET based resistive keeper circuit using 45nm PTM FinFET model which reduces the contention between pull down network and keeper device using the special feature of four terminal FinFET (capacitance merging among...
This research proposed a new design of memory cell of 7T SRAM using 16nm and 45nm (Arizona State University Predictive Technologies Model) PTM models. The memory cell provides larger static noise margin in hold state and a better read operation by controlling drain induces barrier lowering (DIBL) effect. With utilization of a single transistor, proposed cell provides stability of the data not only...
Polymeric optical waveguides have recently drawn a great interest in the fabrication of many functional optical devices. Photolithography is the widely used technique for the fabrication of such waveguides. To facilitate low-cost manufacturing and to achieve high reproducibility, determination and control of the process parameter in the different fabrication steps is very important. However, the mathematical...
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