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As the demand expanding for high electrical performance, high pin count and low cost, the copper pillar bump packaging has been extensively used in recent years. However, the drawback is that copper pillar bump can introduce high stress, especially on low-k chip. In this paper, finite element method was adopted to optimize the structure of copper pillar bump, aiming at relieving the stress of low-k...
Crosstalk between the interconnects cause serious electromagnetic interference (EMI). The high density interconnects, including redistribution layers (RDLs) and through-silicon-vias (TSVs) in silicon interposer, require effective crosstalk-reduction signaling schemes. In this paper, a novel co-planar waveguide (CPW) RDL structure, where the ground lines directly contact the silicon substrate without...
Electrochemical Atomic Layer Deposition (EC-ALD) has been used to fabricate three different superlattice structures of CdTe/PbTe thin films on ITO coated glass: (CdTe20/PbTe20)3, (CdTe10/PbTe20)3 and (CdTe5/PbTe20)3. These are intended to serve as the absorber layer of a solar cell. In our experiments, Cyclic Voltammetry (CV) and current monitoring helped us obtain appropriate deposition potentials...
Just in few years, three-dimensional (3D) packaging technologies have attracted much more attention. With emergence of through-silicon via (TSV) technology, silicon-based device integrations, the TSV's, have become the main stream of 3D packaging technologies. TSV's can be further classified as 2.5D and 3D TSV's. For 2.5D TSV package assembly, since multiple components involved, there are normally...
CdTe/PbTe superlattice films are promising materials to serve as the absorber layer of solar cells. The aim of this study was to fabricate CdTe/PbTe superlattice films on Indium Tin Oxide (ITO)-coated glass substrates using Electrochemical Atomic Layer Deposition (EC-ALD). Cyclic voltammetry (CV) and current monitoring helped us obtain appropriate deposition potentials. The chemical composition of...
In package-on-package (PoP) manufacturing, warpages on both top and bottom packages are concerned. Excess warpage causes solder joint opening, and results in the electrical connection failure of the assembled module. Many parameters of materials, geometry, and process contribute to the warpage of the package. The objective of this paper is to investigate effects of these parameters on the warpage...
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