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Interconnect design has recently become one of the important factors that affect the circuit delay and performance especially in the deep submicron technology. The modelling of interconnects is typically based on using Elmore definitions of the delay time and rise time. So, a general formula for Elmore delay time and rise time in the fractional order domain are presented in this work. It is found...
This paper describes an energy efficient boot-strapped CMOS inverter for ultra-low power applications. The proposed design is achieved by internally boosting the gate voltage of the transistors (via the charge pumping technique), and the operating region is shifted from the sub-threshold to a higher region, enhancing performance and improving tolerance to PVT variations. Despite the proposed bootstrapped...
The effect of crosstalk avoidance codes on the throughput of fixed width communication channels is studied. Closed form expressions of the throughput which incorporate the dimensions of the interconnects and the wiring overheads incurred by such techniques are derived for lines under different buffering conditions. These formulae are utilized to optimize the bandwidth of constrained-area parallel...
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