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We present a reconfigurable neural processor for real-time simulation and prediction of opto-neural behaviour. We combined a detailed Hodgkin–Huxley CA3 neuron integrated with a four-state Channelrhodopsin-2 (ChR2) model into reconfigurable silicon hardware. Our architecture consists of a Field Programmable Gated Array (FPGA) with a custom-built computing data-path, a separate data management system...
Technology scaling is leading to extreme thermal challenges that make worst-case cooling system design unfavourable. On the other hand, on-chip communication, in terms of Network-on-Chip (NoC) workload, is expected to dominate Systems-on-Chip as a major heat source. In this paper a Runtime Thermal Management (RTM) design implementation for NoCs is proposed. Dynamic Programming Network (DPN) is introduced...
The computation of two-dimensional Discrete Cosine Transform (2-D DCT) in image and video compression standards involves specific level of precision and high degree of complexity. This paper introduces two architectures, taking into consideration accuracy, power consumption and speed. The proposed architectures are implemented using the Xilinx system generator on the Virtex5 5vlx50tff1136-3 Xilinx...
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