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An 8-bit 4 GS/s 8-channel time-interleaved successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta-stability immunity technique is proposed, which utilises pre-installation to eliminate uncertain decision. The technique has negligible design overhead in terms of power and silicon area. The ADC chip was fabricated...
VCO is commonly used in time mode ADC to convert analog input voltage to time/phase information, where the time/phase information is subsequently converted to digital code using time-to-digital converter. Although high speed high resolution time-to-digital converters are currently available, the inherent nonlinear property of VCO however has become the bottle neck for time mode ADC. In this paper,...
This paper proposes a new approach to high speed pipelined A/D converter design. This technique combines a known subranging technique into pipelined architecture. A 8-bit 100 MSample/s subranging pipelined analog-to-digital converter (ADC) is implemented using this technique. The calibration techniques used are namely digital error correction, redundancy, and coarse and fine synchronization. To validate...
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