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This paper evaluates the impacts of Transient Voltage Collapse (TVC) Write-Assist on the GeOI and SOI FinFET SRAM cells with global and local random variations. With the TVC Write-Assist, the Write-ability and variation tolerance of GeOI and SOI FinFET SRAM cells are improved. The temperature dependence of data retention time is different between the GeOI and SOI FinFET SRAM cells. The maximum TVC...
A process, voltage and temperature (PVT) sensors with dynamic voltage selection are proposed for environmental management in the ultra-low voltage dynamic voltage and frequency scaling (DVFS) system. The process and voltage (PV) sensors initially monitor the process variation. With known process information, PV sensors can real-time provide voltage variation status. The temperature sensor has six...
This paper analyzes stability and variability of Ultra-Thin-Body (UTB) SOI subthreshold SRAMs considering Line-Edge Roughness (LER), Work Function Variation (WFV) and temperature sensitivity. The intrinsic advantages of UTB SOI technology versus bulk CMOS technology with regard to the stability and variability of 6T SRAM cells for subthreshold operation are analyzed. Compared with LER, WFV causes...
This paper analyzes stability and variability of ultra-thin-body (UTB) SOI subthreshold SRAMs considering line-edge roughness (LER), work function variation (WFV), and temperature sensitivity. The intrinsic advantages of UTB SOI technology versus bulk CMOS technology with regard to the stability and variability of 6T SRAM cells for subthreshold operation are analyzed. Compared with LER, WFV causes...
Negative bias temperature instability (NBTI) has become an important cause of degradation in scaled PMOS devices, affecting power, performance, yield and reliability of circuits. This paper proposes a scheme to detect PMOS threshold voltage (VTH) degradation using on-chip slew-rate monitor circuitry. The degradation in the PMOS threshold voltage is determined with high resolution by sensing the change...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
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