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The feasibility of nano-scale strained-Si technologies for low-power applications is studied. Static and dynamic power for strained-Si device is analyzed and compared with conventional bulk-Si technology. Optimum device design points are suggested, and strained-Si CMOS circuits are studied, showing substantially reduced power consumptions. The trade-offs for power and performance in strained-Si devices/circuits...
The device/circuit performance of strained-Si (SS) MOSFETs including strained-Si channel-on-insulator (SSOI) is assessed via a physics-based compact model calibrated against fabricated 70 nm strained and unstrained (control) Si devices. With emphasis on SS device specific features, mobility enhancement and band offsets, and SOI advantages, dynamic floating-body effects and no areal junction capacitance,...
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