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It is believed that resistive open faults can cause small delay defects at wires, contacts, and/or vias of a circuit. However, it remains to be elucidated whether any methods could diagnose resistive open faults. We propose a method for diagnosing resistive open faults by using a diagnostic delay fault simulation with the minimum detectable delay fault size. We also introduce a fault excitation function...
We propose a testable design method of level shifters inside a liquid crystal display driver IC. The design method enables us to detect open defects in level shifters by supply current testing that are difficult to be tested by voltage testing. Also, we show by circuit simulation that more resistive open defects may be detected by supply current testing than voltage testing, if the level shifter is...
A built-in-current sensor (BIC sensor) is proposed whose IDDQ limit is able to be adjusted in each IC test. IDDQ tests of identical IDDQ limit can be realized with the current sensor, even if process variation occurs in the sensor. Also, an IDDQ test method is proposed for ICs, in each of which the BIC sensor is implemented. It is shown by some experiments that IDDQ limit of 10mu A will be able to...
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