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This paper introduces a 401–457 MHz BFSK transmitter (TX) architecture that utilizes mixing and image rejection techniques to generate the two carrier frequencies for BFSK transmission. The proposed architecture enables low power consumption for a wide range of data rates by avoiding fast settling time requirements for the frequency-locked loop. Simulations indicate that the TX designed in 130nm CMOS...
This paper presents a 12-Gb/s power-efficient voltage-mode driver for multi-standard serial-link applications. The proposed driver combines the advantages of voltage-mode drivers and those of variable-output-swing ones into a single architecture for multi-standard operation. This is achieved by having a reconfigurable pull-up network and a fixed shared pull-down network. In addition, this technique...
A 4-channel 4-bit flash analog-to-digital converter is presented with 10Gbps sampling speed and a figure-of-merit of 182 fJ/conversion-step. It uses a conventional clocking scheme, along with a modified sample-and-hold and comparator chain circuits that reduce the overall ADC power consumption, and enhances both the resolution and accuracy without the need for any digital calibration. The ADC is designed...
A fast phase alignment algorithm using successive approximation register (SAR) is proposed for all-digital phase interpolator (PI)-based clock and data recovery circuits (CDR). The SAR algorithm is performed at the beginning of data reception allowing PI-based CDRs to achieve phase lock in few tens of bit-periods. Further phase tracking and data recovery is done by a conventional PI-based CDR to avoid...
This paper presents a systematic methodology for exploring possible processor arrays of scalable radix 4 modular Montgomery multiplication algorithm. In this methodology, the algorithm is first expressed as a regular iterative expression, then the algorithm data dependence graph and a suitable affine scheduling function are obtained. Four possible processor arrays are obtained and analyzed in terms...
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