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A second-order Gm-C low-pass filter with a novel large-signal linearization method for operational transconductance amplifiers having low supply voltages is presented. The design technique uses a combination of unbalanced resistively degenerated differential pairs and adaptive biasing to extend the linear range. The presented unity-gain biquad filter cell is intended to be used as a building block...
A low-power current-reused LC VCO circuit is implemented in 65-nm CMOS technology. The VCO covers frequency ranges (9.2 → 10.4) GHz and (10.6→12.4) GHz. The VCO core consists of two parallel active sections to adapt Gm with the operating frequency. Adaptive body-biasing technique using a new amplitude detector circuit is proposed. Switched varactor-bank circuit with boosted on-voltage is implemented...
A 4-channel 4-bit flash analog-to-digital converter is presented with 10Gbps sampling speed and a figure-of-merit of 182 fJ/conversion-step. It uses a conventional clocking scheme, along with a modified sample-and-hold and comparator chain circuits that reduce the overall ADC power consumption, and enhances both the resolution and accuracy without the need for any digital calibration. The ADC is designed...
A charge pump circuit to minimize current mismatch and current variation over a wide voltage compliance range is proposed. A feedback loop is used to cancel both deterministic and random mismatches between charging and discharging current to minimize PLL reference spurs and static phase offset. A current compensation circuit is used to minimize current variation to avoid bandwidth variation and loop...
This paper presents a low-power automatic supply multiplexer for reconfigurable step-up/down switching DC-DC converters. The multiplexer continuously compares the input and the output voltages. It then tracks and selects the higher voltage to be used for substrate biasing and supplying gate drivers. This reduces leakage current through substrate diodes and also reduces conduction losses of the driven...
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