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Many routing protocols make some assumptions on the correctness of the routing information in the router. This at times allows faults and malicious attacks in the networks. This paper describes a class of networks based on modified line graphs with many features to authenticate the data and controls of the message routing, and having properties of the shortest diameters and easy shortest path calculations...
Shortest path determination in a class of optimally fault tolerant networks designed using modified line graphs is described here. Appropriate node naming allows the shortest paths to be determined in 0(log n) steps. This is applicable even in the presence of node failures, without loops or backtracking. The stretch of the network is maintained at the theoretically minimum value possible of one.
Summary form only given: Embedded memories have become the fastest growing segment of Systems on Chip (SoC) in recent years. According to the International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing SoC chip area in the future, approaching 94% within one decade. Hence, these memories will severely impact all aspects of SoC manufacturing including...
Negative Bias Temperature Instability (NBTI) has become an important reliability concern for nano-scaled Complementary Metal Oxide Semiconductor (CMOS) devices. In this paper, we present an analysis of temperature impact on various sub-processes that contribute to NBTI degradation. We demonstrate our analysis on 90nm industrial design operating in temperature range 25-125?? C. The key temperature...
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