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This paper presents initial results of a research in the short-term optimal scheduling on the photolithography station in wafer fabrication, which usually acts as a bottleneck station with multiple machines. It is desirable to minimize tardiness without loss the bottleneck utilization while today's wafer fabs are striving to maximize on delivery to their customers. Computational efficiency is one...
Based on the analysis on the scheduling characteristics of the semiconductor manufacturing fabrication lines, we propose a TOC(Theory-of-Constraints) combining ACO(Ant Colony Optimization) sequencing method. The method firstly determines the bottlenecks of a semiconductor manufacturing fabrication line, and then applies an ACO algorithm to obtain the optimized jobs processing priority sequence of...
In this paper, it is firstly noted that the scheduling of a semiconductor wafer fabrication facility (fab) has its special complexities, such as large scale, a mixed of different processing types, unbalanced production facilities, short-term efficient scheduling period, non-zero state at the decision point time, etc. Secondly, the scheduling model for a wafer fab, composed of a machine set, a task...
CPC is a compound priority control strategy used for scheduling semiconductor wafer fabrication. The compound priority of wafers is calculated according to their current processing step, to the amount of wafers waiting for processing in current step buffer, in upstream step buffer, and in downstream step buffer. Wafers with the highest compound priority are dispatched to certain machine to be processed...
A modified difference Hopfield neural network is proposed to overcome the multiple local minimum problem of normal difference Hopfield neural network. On conditions that the modified Hopfield neural network works in a parallel mode and its interconnection weight matrix is negative, it has only one stable state, and the stable state can make its energy function reach to its only minimum. On the basis...
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