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An approximate computing method for chrominance data of the video/image sequences is proposed in this paper, which is implemented in one hybrid cache architecture. This approach fully exploits the fact that the sensitivity of chrominance is much lower than that of luminance to reduce off-chip memory access of chrominance data. For the 4:2:0 image format, the proposed approximate computing method can...
In this paper, a hybrid cache architecture with high versatility and a wide range of applications is proposed, which is effective in image and video processing. Meanwhile, a new 2D-based prefetching scheme for image and video processing, fully exploiting two dimension data locality, is used in this cache. In this scheme, Prefetching Address Generation (PAG) and Prefetching Time Generation (PTG) are...
In this paper, a simple, efficient, low power off-chip memory design is proposed, which fully exploits the features of DRAM memory and video application, as well as overcomes the drawbacks of algorithm complexity and system modification of embedded compression, which is a popular way to decrease power consumption of the off-chip memory. The integration of the scheme into video decoder will not involve...
A novel lossless frame recompression method and an efficient memory address mapping scheme for frame storage are proposed, which can reduce the Read/Write and row activation operations of the external memory. The proposed scheme has been verified with MPEG-2 based HDTV video decoder. Without video quality degradation and the increasing of reading bytes from off-chip memory, the number of bytes writing...
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