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Multi-stage latency adders based on different prediction schemes have been proved promising to enhance the circuit performance with negligible overhead. This paper presents a novel predictor exploiting both the detection and the sequence-dependence between the successive calculations. The detection of carry-kill pattern of the input data can lower the probability of the operation with multiple clock...
A novel circuit architecture for variable latency adder based on present and transitional states prediction (PTSP) method is presented in this paper, for taking the low power benefits of voltage-over-scaling. With the scaling down of CMOS technology, failure from process variation and high power consumption has become severe problem in VLSI design and the traditional conservative methodology is about...
A programmable DCO-based fast-locking clock generator is presented. With a resettable DCO, the clock generator achieves similar jitter performance as conventional MDLL and avoids the initial delay constraints by resetting the output clock every two reference cycles. Compared with the previous work, a shorter locking time is obtained. The proposed clock generator is simulated with generic 1.8 V-0.18...
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