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This paper presents a 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme which has no phase noise degradation. The controllable loop filter enables the CDR circuit to change the operation mode without the output phase noise degradation and the stability problem. The modified half-rate linear phase detector reduces the phase error between the data and clock. A tested...
This paper presents a high resolution two-step gated-ring oscillator (TSGRO) time-to-digital converter (TDC) in an all digital phase-locked loop (ADPLL). TSGRO-TDC consists of a coarse step and a fine step gated-ring oscillator (GRO) TDC to achieve a high resolution. An edge aligner is used in the fine step GRO-TDC to enhance a first-order noise shaping property. A meta-stability free selection logic...
A DLL with a second order duty cycle corrector which consists of a low pass filter and an integrator is presented. This paper shows the analysis and the design of the second order DCC for loop stability and low jitter. The DLL implemented in a 0.13mum CMOS process achieves an output duty error below plusmn1.6% within plusmn25% external input duty error. It has a 29.2 ps peak-to-peak jitter and a 3...
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