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This paper presents an 18-to-23 GHz sub-harmonically injection-locked all-digital PLL (SIL-ADPLL). It adopts the proposed injection-locked frequency divider aided adaptive injection timing alignment technique and uses a proposed (UP-DN) block to adjust the injection timing adaptively at output frequency higher than 20 GHz with low power consumption. A new pulse generator is proposed to relax the trade-off...
This paper proposes a wideband subharmonically injection-locked PLL (SILPLL) with adaptive injection timing alignment technique. The SILPLL includes three main circuit blocks: one-oscillator-period constant-delay (OOPCD) divider, timing-adjusted phase detector (TPD), and pulse generator (PG). The proposed injection timing alignment technique can align the injection timing adaptively in a wide range...
A novel wideband subharmonically injection-locked PLL (SILPLL) is proposed. It adopts a new injection timing alignment technique to adjust injection timing adaptively in wide range of the output clock frequency. A proposed pulse generator is used for half-integral injection to relax the trade-off between phase-noise of SILPLL and output frequency resolution. The SILPLL is implemented in 65 nm 1P9M...
A single-loop second-order 3 bits ΔΣ modulator in 180 nm standard CMOS is presented. The design is intended to achieve high linearity in low-voltage low-power environment. The modulator achieves 89-dB SNDR and 98-dB SFDR in 20Hz~16kHz signal bandwidth, while the power consumption is 210 μW under 1-V supply voltage.
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