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A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementary elements to solve the continuity equation for minority carriers in the volume based on the finite-difference method. A substrate parasitic network...
When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a spice-based approach to characterize electrical key parameters of a passive protection directly within standard IC design flow avoiding time consuming TCAD simulations. Our methodology consists...
This paper presents a new approach for substrate parasitic current simulation in smart power integrated circuit. A new compact modeling approach developed in previous work has been used to create an equivalent substrate schematic. The latter is composed of new components having the peculiarity not to fully recombine minority carrier at their boundary. By the interconnection of these special components...
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