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This work analyzes the effect of the different design stages on the failure rate of circuits implemented in FPGAs. A bitstream-based SEU emulation platform is used to inject faults in order to analyze the critical bits of the circuit. Experiments are done on two different testbenchs, an FIR filter and a CORDIC chain. Tests consist on loading different variations of the designs in order to estimate...
Field Programmable Gate Arrays (FPGAs) are commonly used in safety-critical and mission-critical systems. In these applications failures are unacceptable, since they can lead to people injured or huge economical losses. Due to Moore's law and the continuous size reduction, electronic devices are able to perform more and more complex functionalities. However, they are becoming more and more vulnerable...
This paper presents a fault injection method for SEU (Single Event Upset) emulation in FPGAs based on loading at the programmable logic a configuration file with an erroneous bit. A "Xilinx Zynq®-7000 All Programmable SoC" device has been used to implement it, which combines a hard microprocessor (Processing System PS) with Programmable Logic (PL). The emulation tool is fully implemented...
In this paper a new SEU (Single Event Upset) emulation method for testing fault tolerant systems in FPGAs is presented. It is implemented on a “Xilinx Zynq®-7000 All Programmable System on Chip (SoC)” device, which combines a hard microprocessor with programmable logic. An important new feature is that an internal hardware configuration interface controlled by this microprocessor is provided. This...
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