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We propose formal means for synthesizing switching protocols that determine the sequence in which the modes of a switched system are activated to satisfy certain high-level specifications in linear temporal logic (LTL). The synthesized protocols are robust against exogenous disturbances on the continuous dynamics and can react to possibly adversarial events (both external and internal). Finite-state...
We consider the problem of synthesizing hierarchical controllers for discrete-time switched affine systems subject to exogenous disturbances that guarantee that the trajectories of the system satisfy a high-level specification expressed as a linear temporal logic formula. Our method builds upon recent results on temporal logic planning and embedded controller synthesis. First, the control problem...
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