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This paper demonstrated a 5GSample/s track and hold amplifier with 65nm CMOS process. For 6bit ADC application, this work has over 42dBc of SFDR to offer a low distorted signal. The source-degenerated source-couple amplifier with peaking inductance is employed to expand the signal swing and bandwidth, while the power dissipation is maintained as low as possible. The measured power dissipation is 48...
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