The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The substrate bias in bulk FinFET devices can be used to increase both the sense margin and retention time in 1T memory cells. For given biasing conditions, a substrate bias can be found where sense margin and retention time are optimal. This substrate bias results from a trade-off between the storage of electrons and holes and the impact of the READ conditions.
Retention times up to 10s at 85°C can be achieved for bulk FinFET 1T-DRAM devices using an optimized biasing scheme which targets the storage of electrons in the fin. The impact of the ground plane doping is investigated and finally the read-out scheme is also demonstrated on SOI FinFET devices.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.