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Retention times up to 10s at 85°C can be achieved for bulk FinFET 1T-DRAM devices using an optimized biasing scheme which targets the storage of electrons in the fin. The impact of the ground plane doping is investigated and finally the read-out scheme is also demonstrated on SOI FinFET devices.
The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins...
For the first time, scaled PMOS MUGFET devices with TiCN/HfO2 gate stack is doped with specific pulsed plasma doping processes. This paper first highlights the key benefit brought by conformal source/drain extensions, demonstrates how pulsed plasma doping process can be tuned to conformal dope very dense fin structures and finally shows that high performance (+24% vs. ion implant reference) multi-gate...
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