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Electronic packages absorb moisture when exposed to uncontrolled humid conditions during manufacturing processes and service life. At high temperatures, the effects of moisture absorption on electronic packages become even more significant. A number of failure modes are caused by moisture effects such as popcorn cracking, delamination, and electrochemical migration. In this study, the effects of moisture...
Stress sensing test chips are a powerful tool for measuring in-situ stresses in electronic packages. In this study, we have applied (111) silicon test chips to perform a variety of measurements of moisture and thermally induced die stresses in flip chip on laminate assemblies. The developed chips incorporated optimized eight-element sensor rosettes that were capable of measuring the complete state...
In this work, we have used test chips containing piezoresistive sensors to characterize the in-situ die surface stress evolution during thermal cycling of flip chip ceramic ball grid array (FC-CBGA) components suitable for microprocessor packaging. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being...
The increasingly complex packaging used in modern workstations and servers transmits a complicated set of mechanical loads to the microprocessor. Increasing die size, high CTE ceramic substrates, lead free solder joints, and ever increasing power requirements have led to increased die stress levels in packaged microprocessor die. Such stresses can degrade silicon device performance, as well as damage...
On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during...
Multi-element resistor rosettes on silicon are widely utilized to measure integrated circuit die stress in electronic packages and other applications. Past studies of many sources of error have led to rosette optimization and demonstrated that temperature-compensated stress extraction should be used whenever possible. In this work, we extend the error analysis to include the inherent uncertainty in...
On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as the stress changes occurring due to thermal cycling. The utilized...
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