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We developed and reported on a 3-D stacked CMOS image sensor (CIS) with a massive number of micro-bump interconnections placed at a narrow pitch between silicon substrates that pushes the envelope of CIS functions. The resistances of the interconnections were measured to be less than one hundredth of an ohm per bump with a test structure. There were, however, a small number of defective micro bumps...
Our 3D stacked CMOS image sensor (CIS) has an ideal global shutter function with 16 million pixels and 4 million micro-bump interconnections placed at a 7.6-εm pitch between two silicon substrates, achieving interconnections with very low resistance. We confirmed the reliability of our 3D stacked interconnection technology by conducting reliability tests, which included heat cycle tests and high temperature...
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