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HV n-/p-LDMOS devices with the source-side extending into bulk-region to evaluate the electrostatic-discharge (ESD) protection robustness by a TSMC 0.25 µm 60 V process are investigated in this paper. After a systematic analysis, the trigger voltage (Vt1) values of the n-LDMOS with the source-side extending into the bulk-end either by uniformly or non-uniformly distributed manners that had decreased...
The effects of leakage-biased voltage (VLB) levels are investigated in this paper, which are set for failure-mode identification on the final fault diagnostic measurement in transmission line pulse (TLP) testing. To identify the effect on electrostatic discharge (ESD) robustness, three types of MOSFET components were employed; namely, low-voltage n-channel MOSFET (LVnMOS) (5 V/0.6 μm), high-voltage...
The impacts of current-path variation on the ESD robustness of nLDMOS devices as the drain-side modulation by a 0.18 μm/40 V process are evaluated in this paper. From the transmission-line-pulsing (TLP) measurement, the secondary breakdown current (It2) of an nLDMOS with the drain-side embedded SCR structure & "pnp" arrangement (DUT-2) increased from 2.498 A up to > 7 A (at least...
Impacts of zapping-voltage step (ΔV) setting on the final fault-diagnostic measurement of transmission-line pulse (TLP) testing are presented in this paper. In order to identify the influence on electrostatic-discharge (ESD) immunity evaluation, three kinds of MOSFET devices are employed, which are the LV nMOSFET (0.6-µm/5-V), HV nMOSFET and HV pMOSFET (1.8-µm/12-V) technologies devices, respectively...
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