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Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated. Constant TSV aspect ratio and constant TSV area penalty scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of power...
The effects of inductive coupling among TSVs within large TSV arrays are investigated in this paper. A comparison of the equivalent inductance of a paired TSV model and arrayed TSV macromodel is presented for three TSV distribution topologies, grouped, lined, and uniform, within the power network. Modified closed-form expressions are proposed to determine the equivalent inductance of a TSV in these...
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