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In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The structure of divide-by-4/5 frequency divider is simplified, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 25% reduction of power consumption is achieved by the proposed unit. In the 32/33...
New design improvement aiming to reduce the power consumption of true single-phase clock-based dual-modulus divide-by-2/3 prescalers is presented. The first latch stages of TSPC FFs are merged to reduce power and capacitance. Also, a pass transistor is introduced to cut off short circuit current. Hspice simulation of the proposed scheme in 40nm process demonstrates best power efficiency and power-delay-product...
In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The proposed design technique is applied to a divide-by-2/3 unit, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 49% reduction of PDP is achieved by the proposed unit.
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