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This paper presents a 2×14bit cartesian Direct Digital RF Modulator (DDRM) in 28nm CMOS. Both AM and PM calibration circuits are introduced to relax matching requirements of the DDRM units which results in a compact and efficient implementation. The DDRM features a memoryless current source based unit cell to avoid complex dynamic digital predistortion (DPD) algorithms. All the units can be tuned...
This paper describes a single op-amp 0+2 ∑Δ architecture and design considerations to achieve 12-b resolution on a 2-MHz bandwidth. The proposed topology combines op-amp reduction and MASH techniques. In particular, the second-order ∑Δ stage uses direct synthesis of the noise transfer function (NTF) and employs only one op-amp. The use of multi-bit quantization on both stages increases the resolution...
This paper presents a second-order 3-bit incremental converter, which uses a novel Smart-DEM algorithm for mismatch compensation of multi-level DAC unity elements. The circuit, fabricated in a mixed 0.18–0.5-µm CMOS technology, achieves more than 17-bit resolution over a 5-kHz bandwidth using 256 clock periods. A single-step chopping of the input stage leads to a residual offset of 9.7 µV. The measured...
This paper describes the design method for highorder multi-bit incremental converters aiming at high resolution (> 14 bits) with Smart-DEM algorithm. Traditional 2nd and 3rd-order incremental ADCs use 1-bit quantizer. These structures lead to long conversion time for each sample to achieve the expected resolution and high power consumption due to the large output swing of the op-amps. Also, the...
The concept of high-order ramp analog-to-digital converter and its design aiming at medium-high resolution (12–14 bits) are presented. Design methods that give rise to various Nyquist rate schemes resembling incremental converters are described. Since for Nyquist rate achieving noise shaping is not the goal, the design care is just maintaining good stability to avoid performance degradation. Different...
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