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This paper presents a fractional-N sub-sampling phase-locked loop (SSPLL) for spread-spectrum clock generator. A digital-to-time converter (DTC) is adopted to facilitate a fractional-N SSPLL. A digital calibration scheme is employed to eliminate DTC gain error. With the calibration method enabled, the PLL is successfully locked and achieves 18.98-dB EMI reduction. This PLL was fabricated in a TSMC...
A low-power continuous-time delta-sigma modulator (CTDSM) incorporating a multi-bit feedback-assisted quantizer (FBAQ) is presented in this paper. The proposed multi-bit quantizer is placed in a negative feedback loop to reduce the signal swing at its input. As a result, the number of comparator required for signal quantization is reduced. Furthermore, the modulator is optimized for low-voltage swing...
This paper proposes a fractional-N PLL with 2-dimensional quantization noise pushing technique to suppress the quantization noise and a fractional spur elimination technique to mitigate fractional spurs. With these techniques, the experimental results show that the quantization noise is reduced by around 30 dB, and the fractional spurs are considerably suppressed. This PLL was fabricated in a TSMC...
A sensor readout circuit employing chopped VCO-based CTDSM is presented in this paper. This VCO-based ADC features direct connection to the sensors to eliminate pre-amplifier. The VCO is designed as a Gm-CCO, which is a Gm stage cascaded with the folded-cascode current-controlled oscillator. The proposed circuit ensures a high input impedance. Furthermore, the main noise and offset contributor, the...
A second-order multi-bit quadrature bandpass continuous-time delta-sigma modulator (QBP-CTDSM) employing a power scaling technique (PST) is reported in this paper for GSM-EDGE/UMTS/DVB-T receivers. This modulator employs operational amplifiers with PST to optimize power consumption among the tri-mode operation. The QBP-CTDSM is fabricated in a 0.18-μm CMOS process. It achieves 81/61.2/60...
This paper presents a 1-V and low-noise readout front-end for biomedical applications. The key to this low-voltage and low-power operation is the current-mode instrumentation amplifier (CMIA). To reject the DC offset, an active-RC integrator with the subthreshold-biased PMOS as high resistance is included in the CMIA and forms the offset cancellation loop. The nested-chopper technique is applied to...
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