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An optimization system which uses the multi-objective evolutionary algorithm based on decomposition (MOEA/D) is presented for sizing second generation current conveyors (CCIIs). The proposed optimization system uses HSPICE as circuit evaluator and its usefulness is highlighted by sizing two CCIIs, which are optimized in voltage and current modes in three parameters: gain, bandwidth and offset, and...
Sensor interfaces are a crucial and power-hungry part in many applications. Research is therefore needed to look for alternative solutions that reduce the power consumption of the interfaces while achieving the targeted accuracy and speed requirements. This invited talk reviews both existing and novel design solutions, based on both voltage-mode and time-mode signal processing. This is illustrated...
In this paper, a fuzzy selection-based differential evolution algorithm (FSBDE) for analog cell sizing is investigated. By combining the selection-based constraint handling method and fuzzy membership functions, a new selection methodology for handling fuzzy constraints is proposed and is integrated with the differential evolution (DE) algorithm to construct FSBDE. FSBDE specializes in solving analog...
In this work, a 10 Mb/s impulse UWB RFID tag in 0.18 mum CMOS is presented. The tag is remotely powered by a UHF signal with a minimum input RF power as low as 14.1 muW. The primary innovation is to employ two different communication links (UWB and UHF) respectively in the uplink and downlink of the tag. This is because the amount of data or instructions from a reader to a tag is small and as a result...
This paper demonstrates a system that performs multi-objective sizing across 100,000 analog circuit topologies simultaneously, with SPICE accuracy. It builds on a previous system, MOJITO, which searches through 3500 topologies defined by a hierarchically-organized set of 30 analog blocks. This paper improves MOJITO's results quality via three key extensions. First, it enlarges the block library to...
In this paper, an efficient technique for monopole antenna size miniaturization is introduced. Base on this idea, %50 antenna area reduction is achievable while antenna performance in terms of Sll is approximately the same and it's even improved in terms of radiation pattern.
This paper presents a methodology for analog designers to maintain their insights into the relationship among performance specifications, topology choice, and sizing variables, despite those insights being constantly challenged by changing process nodes and new specs. The methodology is to take a data-mining perspective on a Pareto Optimal Set of sized analog circuit topologies, then doing: extraction...
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