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In All-digital IF receiver, the timing synchronization signal, due to inter-symbol interference will produce a high error rate, and then through the equalizer, eliminate inter-symbol interference. This paper uses CMA (constant modulus algorithm) to eliminate inter-symbol interference, and uses pipeline structure and complex multiplication optimization to improve processing speed, and save resources...
A timing synchronization system for QAM signal is proposed in our work. Both Gardner algorithm and Farrow-structure are included to optimize our design. The synchronization system can be used separately before the carrier synchronization and not sensitive to carrier phase. The system of 128 QAM signal is simulated and implemented in FPGA platform, which proves that be effective, and has good performance.
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