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Signal integrity issue has become more and more important in recent years. In order to have a good signal quality, many aspects in a digital channel must be carefully considered. In this paper we compare the effects of non-ideal output driver and different power distribution networks (PDNs) on the signal integrity. The channel performance variation under different driving bit rates is also analyzed...
Algorithms featuring fast and accurate estimation of worst-case eye diagram have been proposed to replace the time-consuming random bit simulation in channel design. However, when the interaction between nonlinear I/O circuits and power distribution network (PDN) noise is included, most of those approaches fail to maintain accuracy. Based on the superposition of multiple bit pattern responses (SMBP)...
Based on two-port measurements, a distributed compact model and an extraction method for the power bus of a high-speed memory chip are proposed. The 1-D model is constructed according to the relative locations of the power and ground pads on the chip. The power bus around each power or ground pad is modeled by a section of resistor-inductor-capacitor (RLC) T-model, and the complete distributed model...
A collection of slides from the authorpsilas seminar presentation is given. P/GBN is one of the key issues for designing high-speed digital circuit with good signal integrity (SI) and EMC performance. Several approaches to eliminate the P/GBN on the power delivery systems are investigated by both numerical simulations and experimental measurement.
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