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A Simulated Annealing Genetic Algorithm (SAGA) with greedy mapping mechanism is developed to solve task partitioning problems in coarse grain reconfigurable systems. A fitness function combined multiple objectives (communication cost, number of partitions and number of bypass nodes) is constructed to optimize the execution time. Experimental results show that SAGA produces better solutions than traditional...
Quadratic permutation polynomial (QPP) interleaver is a contention-free interleaver which is suitable for parallel turbo decoder implementation. In this paper, a systematic recursive method to design configurable QPP interleaving multistage network is proposed based on the property of QPP. Due to the nature of recursion, the proposed network for 2n-level parallel turbo decoder can be used for any...
Morphosys is a reconfigurable single instruction multiple data (SIMD) architecture mainly composing of host core processor, reconfigurable cells array, frame buffer, context memory and direct memory access (DMA) module. As a common SIMD-based coarse-grained reconfigurable architecture, each context configuration and operation is based on the whole row or column function, which may be inefficient in...
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