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This paper presents a 10 bit charge redistribution successive approximation analog-to-digital converter (ADC) for integrated digitally controlled DC–DC converters. A timing efficient implementation of a window function is proposed, where only a reduced input range is converted. A redundant search is applied to overcome the speed limitation of the analog components. The window mode enables further...
A 10 bit charge redistribution SAR ADC for digitally controlled DC-DC converters is presented. A redundant search is applied to increase the conversion rate. The required digital circuitry for calculation of the redundant search tree allows implementation of a window mode, where only a reduced input range is converted. The window function enables further speed enhancement without an increase of clock...
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