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Dual-Vt technology is effective in leakage reduction and has been implemented in industry EDA tools. However, on-chip temperature is regarded as uniformly distributed over the chip, with a pre-assumed value. This assumption does not hold for designs in the deep sub-micron domain as on-chip temperature variation becomes more and more significant. As a result, treating temperature as a constant will...
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-a- chip, in particular DSP systems, can greatly improve performance through parallelism. On the other hand, dynamic voltage scaling (DVS) has been shown to be one of the most effective low power design techniques and multiple supply voltage system is among the most practical...
The increasing leakage power and chip temperature in microprocessors are adversely affecting the performance and power consumption in real-time embedded systems. However, the traditional dynamic voltage scaling (DVS) technique, a popular and effective low-power design method, does not include the leakage and temperature impacts. In this work, we consider these two impacts when designing DVS-enabled...
In this paper, we study the interdependency between leakage energy and chip temperature in real-time systems. We observe that the temperature variation on chip has a large impact on the system's leakage energy. By incorporating the temperature information, we propose an online temperature-aware leakage minimization algorithm for real-time systems. The basic idea is to run tasks when the system is...
A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the primary copy. If there is no fault, the secondary processor terminates its execution. Otherwise, should the fault occur, the second processor continues and completes the application before its deadline. In this paper, we study...
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