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This paper proposes an FPGA implementation of a simple and reliable method for real-time peak detection of time series data. Focusing on an existing off-line method called Automatic Multiscale Based Peak Detection (AMPD), we show, how the original AMPD algorithm is modified to be an on-line method and how it is applied on an FPGA. To validate the accuracy of our design, simulation results in a case...
This paper deals with the real-time FPGA implementation of the posterior system state estimation in dynamic state-space models using a particle filter. The system is constructed by parallel resampling (FO-resampling) algorithm on a stream-based architecture. In particular, the system consists of three steps: prediction, likelihood calculation and resampling. Since the resampling is accomplished in...
In order to apply the CPU to the control system for the renewable energy plant which is usually installed in the isolated place, there are a lot of issues e.g. the cooling, the power conservation and the parts exchange with the device life cycle. The undetectable dangerous error of the control system is also a big issue for such the isolated plant with the long term operation, because it causes the...
For the renewable energy system, the power conservation and the low heat emission of the control system are big issue. Since those energy plants are installed in the natural environment which is inconvenient for the maintenance, it is very important that the control systems are supplied and maintained for long term without any development risk. The performance of the current CPU depends on the number...
The data center of the cloud which supports the recent communications infrastructure requires the high reliable control systems in order to control its enormous electric power and exhaust heat. It is important to reduce the energy wasted by the control systems. The FPGA is watched because of the low energy, the long sustainability, and the simple architecture. It is clarified that the FPGA realizes...
This paper proposes an FPGA-based soft core processor architecture equipped with a configurable accelerator to speed up GF(2m) arithmetic for elliptic curve cryptography (ECC) systems. Focusing on the fact the number of operations required for GF(2m) arithmetic is influenced by the relationship between the irreducible polynomial and the machine word size, we propose an approach where the word size...
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