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In this publication, techniques for high power handling capability of RF switches in bulk CMOS are investigated and compared. These allow reconfigurable power amplifiers (PAs) or radio front ends for Watt level communication standards if combined with approaches for high isolation. Special care is taken to assess the applicability of the solutions for monolithic integration in scaled CMOS processes...
This work reports on the considerations for building RF switches in deeply scaled CMOS. As demonstrator single pole single throw (SPST) switches in a standard 65 nm technology are designed and measured. Goal of this design is lowest insertion loss while achieving high power handling capability, linearity, and robustness. For the novel design of switch variant Dev 1 0.8dB of insertion loss, 30dBm of...
This work reports on methods and dependencies for the design of low insertion loss single pole single throw (SPST) switches in 65nm CMOS with triple well transistors. Two different switch types are investigated and implemented. The series switch has less than 1dB insertion loss at 1.8GHz and a 1dB input compression point (P1dB) of 28.8dBm. The shunt switch has less than 0.4dB insertion loss at 1.8GHz...
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