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A 1.02nW current reference is designed with only PMOS transistors, thereby providing inherently low process variation and enabling trim-free operation. Thirty-two measured chips from 5 corner wafers in 180nm CMOS technology show an untrimmed within-wafer spread (σ/μ) of 1.6% and across-corner wafer-to-wafer spread of ±4.7%. The measured average temperature coefficient is 282ppm/°C from −40°C to 120°C...
The mismatch of current sources is caused by the circuit error and the process variation. Introducing the channel length modulation λ to the Pelgrom model for variation analysis, we describe a new ΔI/I model of current sources. To make it clear what variation parameter influences the mismatch, we implemented a test chip on 90nm process technology, where we can collect the characteristics variation...
This paper addresses the problem of transistor decomposition, which can be used in high accuracy analog applications and structured analog design. We made a test chip to verify the feasibility of the transistor decomposition because of the lack of theoretical support. The DC/AC measurement results from the chip suggests that the decomposition, the transistor channel tuning, as well as structured analog...
Size of STI wells is another significant factor to affect the stress magnitude (device mobility) besides size of transistor active regions. In this paper, we present a technique for improving device mobility in the critical path via global STI well width adjusting following the chip placement stage. The methodology formulates the original device mobility enhancement problem as a series of convex geometric...
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