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In this article, the effect of Instructions on the delay of the execution unit of the pipeline processor is examined. Better than Worst-Case scenarios set the clock frequency faster than the nominal one and avoid potential timing violations. In this work, the effective parameters that could predict timing violations in the processor are examined. It will be shown among different parameters, in most...
In this paper, we propose a signature based pruning technique to facilitate the debugging of multi-threaded processors. To accomplish this, a pipelined implementation of the multi-threaded processor model is checked for correspondence against the specification model based on flushing proof. Then, a two-stage signature oriented pruning method is proposed to avoid the space explosion problem caused...
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