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Dynamic reconfiguration of multiprocessor platforms is an important challenge for System-on-Chip designers. Addressing this issue is mandatory in order to manage the increasing number of applications and execution conditions that multiprocessor platforms have to face. In this paper, a novel configuration infrastructure for the UDec multi-ASIP turbo decoder architecture is presented. Our approach leads...
Adaptation of hardware in relation to the requirements of a specific application is well known and investigated in the domain of Field Programmable Gate Arrays (FPGA) based reconfigurable system architectures. In these system approaches, a number of predefined blocks, mainly accelerators for processors, are loaded from an external storage and are transferred to the FPGA configuration memory in order...
In this paper we introduce the concept for an embedded performance monitor of PCI Express links. This PCI Express Performance Monitor (PPM) enables the analysis of several properties (e.g. amount of available credits), without affecting the performance of the monitored link. By including a PPM in an embedded system it is possible to avoid the need for high cost PCI Express measurement and analyzing...
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