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Deadlock is a common problem in 3D networks-on-chip. In this paper, we propose a lightweight and deadlock-free turn-guided routing scheme named TURO without requiring any virtual channels, which is a minimal routing guided by a new 3D turn model NeoOE. The theoretical analysis and experimental results show that TURO possesses improved adaptivity, higher performance and lower overhead compared with...
The poor yield of current available processes for Through-Silicon Via (TSV) fabrication leads to serious influence on the robustness of the vertical communications in 3D NoCs. The fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of 2D NoCs. In this paper, we propose a high-performance reliable routing scheme HARS, which is deadlock-free by obeying...
Fault-tolerant routing is usually used to provide reliable on-chip communication for many-core processors. This paper focuses on a special class of algorithms that do not use virtual channels. One of the major challenges is to keep the network deadlock free in the presence of faults, especially those locating on network edges. State-of-the-art solutions address this problem by either disabling all...
Applications' traffic tends to be bursty and the location of hot-spot nodes moves as time goes by. This will significantly aggregate the blocking problem of wormhole-routed Network-on-Chip (NoC). Most of state-of-the-art traffic balancing solutions are based on fully adaptive routing algorithms which may introduce large time/space overhead to routers. Partially adaptive routing algorithms, on the...
The Network-on-Chip (NoC) meshes are limited by the reliability constraint, which impels us to exploit the fault tolerant routing. Particularly, one of the main design issues is minimizing the loss of non-faulty routers at the presence of faults. To address that problem, we propose a new fault tolerant routing, which has the following two distinct advantages: First, it keeps a network deadlock-free...
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